This application relies for priority upon Korean Patent Application No. 2001-1892, filed on Jan. 12, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a method of forming a semiconductor device and, more particularly, to a method of forming a semiconductor device including a memory cell area having a plurality of memory cells and a peripheral circuit area for writing and reading data in the memory cells on a semiconductor substrate.
2. Description of the Related Art
In memory devices, a voltage must be applied to gate electrodes, source/drain regions, and bulks in order to drive transistors, basic elements of memory devices such as dynamic random access memories (DRAMs). For this reason, contacts formed on source/drain regions must have very low resistance. Otherwise, high contact resistance decreases current drivability. However, as design rules decrease with an increase in integration of DRAMs, the size of contact holes become reduced as well. As a result, contact resistance undesirably increases.
In a stack-type capacitor in DRAM devices, a decrease in the size of the chips increases the height of the capacitors that in turn increases the depth of the contact holes formed on the source/drain regions. Thus, the contact holes are not formed completely and contact resistance increases. Consequently, it is now more difficult to form interconnections.
In order to easily form contact plugs and reduce contact resistance, a method for forming contact pads or landing pads before forming metal contacts has been attempted. U.S. Pat. No. 5,949,110 discloses the structure of a DRAM where contact pads are formed in a peripheral circuit area as well as in a memory cell area. The structure and fabrication methods for forming the disclosed contact pads will be described with reference to FIG. 1.
As shown in FIG. 1, the DRAM includes n-type transistors CN and capacitors 150 in a memory cell area C and n-type transistors PN in a peripheral circuit area P. Contact pads 140, 140xe2x80x2, 142, and 142xe2x80x2 are formed on source/drain regions 120 and 120xe2x80x2 of the transistors CN and PN. The contact pad 140 connected to the source/drain region 120xe2x80x2 in the memory cell area C serves as a bit line, and the contact pad 142 connected to the source/drain region 120 in the memory cell area C serves as a lower electrode of the capacitor 150. The contact pads 140xe2x80x2 and 142xe2x80x2 in the peripheral circuit area P are each connected to metal interconnections 170 via contact plugs 160. Contact pads 140, 140xe2x80x2, 142, and 142xe2x80x2 are concurrently formed in their respective regions. Specifically, the contact pad 140 in the memory cell area C and the contact pad 140xe2x80x2 in the peripheral circuit area P, that is, first contact pads, are formed concurrently. The contact pad 142 in the memory cell area C and the contact pad 142xe2x80x2 in the peripheral circuit area P, that is, second contact pads, are formed concurrently. The first and second contact pads are made by depositing and patterning a polysilicon layer on a semiconductor substrate. Interlayer insulating layers 141 are interposed between contact pad 140 and contact pad 142 so that they are not in contact with one another, and similarly between contact pad 140xe2x80x2 and contact pad 142xe2x80x2.
The above-described method for forming the contact pads has several problems. First, when a polysilicon layer is patterned in the formation of the first and second contact pads, the source/drain regions of the transistors are damaged by etching, thereby deteriorating device characteristics. To prevent this, the contact pads are required to extend over field oxide layers. However, in this case, it is difficult to ensure the minimum line width that is required for a photolithographic process. Second, the bit line and the bit line contact pad are concurrently formed. In other words, bit lines are generally used as interconnections in a sense AMP region, and thus it is difficult to form the bit line and the bit line contact pad at the same time in the sense AMP region. Third, the heights of the first and second contact pads are different from each other, and thus subsequent planarization is difficult. Also, when contact holes are etched to form contact plugs on the contact pads, difficulties due to a step difference occur. If different conductive type transistors, i.e., an n-channel transistor and a p-channel transistor, are concurrently formed in the peripheral circuit area, there is an additional problem with the application of the method of forming contact pads disclosed in U.S. Pat. No. 5,949,110.
As described above, in memory devices such as DRAMs, the conventional method for forming contact pads on source/drain regions of transistors in a memory cell area and a peripheral circuit and to easily form contact holes has many problems to overcome.
The present invention provides a method of forming a semiconductor device where contact pads connected to source/drain regions of transistors in a memory cell area and a peripheral circuit are concurrently formed.
The present invention also provides a method of forming a semiconductor device where contact pads are formed of metal to realize low contact resistance on source/drain regions of transistors in a memory cell area and a peripheral circuit.
In addition, the present invention provides a method of forming a semiconductor device where contact pads on source/drain regions of a transistor in a peripheral circuit are formed of metal.
Accordingly, in the method, isolation layers are formed to define a memory cell area and a peripheral circuit on the semiconductor substrate and to isolate each device. A first conductive type transistor is formed in the memory cell area and a first conductive type transistor and a second conductive type transistor are formed in the peripheral circuit by forming source/drain regions and gate electrodes having sidewall spacers and first etch stopping layers on active areas in the memory cell area and the peripheral circuit. An interlayer insulating layer is formed on the transistors. Plugs are formed by patterning the interlayer insulating layers, opening the source/drain regions of the transistors in the memory cell area and the peripheral circuit, and filling the openings with a conductive material. Contact pads are concurrently formed on the source/drain regions in the memory cell area and the source/drain regions in the peripheral circuit by etching the plugs and the interlayer insulating layers and then node-separating the plugs.
According to a first embodiment, the conductive material is preferably doped polysilicon. During the formation of plugs, the interlayer insulating layer is etched to open the source/drain regions of the first conductive type transistors in the memory cell area and the peripheral circuit. First conductive type polysilicon layers are formed on the opened source/drain regions of the first conductive type transistors. The interlayer insulating layer is etched to open the source/drain regions of the second conductive type transistor in the peripheral circuit. A second conductive type polysilicon layer is formed on the opened source/drain regions of the second conductive type transistor.
According to the first embodiment of the present invention, a second etch stopping layer is formed on the transistors. The second etch stopping layer has lower etching selectivity than the interlayer insulating layer during the formation of the plugs. The second etch stopping layer is preferably a silicon nitride layer.
According to the first embodiment of the present invention, forming the contact pads comprises etching back the conductive material in the memory cell area and the peripheral circuit, and etching back the interlayer insulating layers in the memory cell area and the peripheral circuit to node-separate the plugs. The contact pads may be formed by chemical and mechanical polishing the conductive material and the interlayer insulating layers to node-separate the plugs.
According to another embodiment of the present invention, isolation layers are formed to define a memory cell area and a peripheral circuit on a semiconductor substrate and isolate each device. A first conductive type transistor in the memory cell area is formed and a first conductive type transistor and a second conductive type transistor are formed in the peripheral circuit by forming source/drain regions and gate electrodes having sidewall spacers and first etch stopping layers on active areas in the memory cell area and the peripheral circuit of the semiconductor substrate. A conductive epitaxial layer, which extends from the source/drain regions onto the isolation layers, e.g., field oxide layers, is formed on the respective source/drain regions. An interlayer insulating layer is formed on the transistors and the conductive epitaxial layer. Plugs are formed by patterning the interlayer insulating layer, opening the source/drain regions of the transistors in the memory cell area and the peripheral circuit, and filling the openings with metal. Metal contact pads are concurrently formed in the memory cell area and the peripheral circuit by etching the plugs and the interlayer insulating layer and then node-separating the plugs.
According to a second embodiment of the present invention, during the formation of the conductive epitaxial layer, the epitaxial layer is formed on the source/drain regions of the semiconductor substrate. First conductive type impurity ions are implanted by forming a photoresist pattern for opening the epitaxial layer formed on the source/drain regions of the first conductive type transistor and then using the photoresist pattern as an implantation mask. Second conductive type impurity ions are implanted by forming a photoresist pattern for opening the epitaxial layers formed on the source/drain regions of the second conductive type transistor and then using the photoresist pattern as an implantation mask. The epitaxial layers are preferably formed of silicon. Preferably, the doping concentration of the epitaxial layers is 1019xcx9c1021 atoms/cm3.
According to the second embodiment of the present invention, node-separation is performed by etching back or chemical and mechanical polishing the metal plugs and the interlayer insulating layer. The metal plugs are preferably tungsten.
In accordance with another aspect of the present invention, first and second gate electrodes having sidewall spacers and etch stopping layers are formed on an active area in the peripheral circuit. An interlayer insulating layer is formed on the first and second gate electrodes. First and second conductive type transistors are formed by forming openings in predetermined portions of the interlayer insulating layer on the active area including the first and second gate electrodes, implanting first and second conductive type impurities into the openings, and forming source/drain regions. A metal layer is formed in the openings, and metal contact pads are formed by node-separating the metal layer.
According to a third embodiment of the present invention, the concentration of the first and second conductive type impurities is preferably 1019xcx9c1021 atoms/cm3, respectively.
According to the third embodiment of the present invention, during the formation of the transistors, a first opening is formed by etching the interlayer insulating layer on the active area including the first gate electrode. A first conductive type source/drain region is formed on the semiconductor substrate by implanting first conductive type impurities into the first opening. A second opening is formed by etching the interlayer insulating layer on the active area including the second gate electrode. A second conductive type source/drain region is formed on the semiconductor substrate by implanting second conductive type impurities into the second opening.
According to the third embodiment of the present invention, the interlayer insulating layers on the active area including the first and second gate electrodes and on the isolation layer between the gate electrodes are opened by etching. A first conductive type source/drain region is formed by implanting first conductive type impurities into the active area including the first gate electrode in the opening. A second conductive type source/drain region is formed by implanting a second conductive impurities into the active area including the second gate electrode in the opening. The source/drain region of the first conductive type transistor is locally connected to the source/drain region of the second conductive type transistor by the metal contact pad.